The present invention relates generally to very large scale integration (VLSI) circuits, and more specifically the invention pertains to a method of packaging wafer scale integration (WSI) devices.
The use of VLSI chips for the miniaturization of complex electronic equipment has brought about new kinds of problems. Wafer scale integration has been a desired packaging alternative primarily because it has the capability for achieving extremely dense integrated circuit packaging and high circuit speeds. Most of the recent wafer scale integration packaging schemes have not been widely used in industry because of the difficulty with integrating packaged devices into a dual composite module design.
The difficulty with integrating packaged devices into a dual composite module design for wafer scale devices is the height difference between the WSI and packaged devices. A typical wafer scale device is 0.025 (in) high while typical packaged VLSI components are 0.080 (in) or more. This leaves little room for the other 5 layers of interconnect boards and PCI layers required for the dual composite module.
The task of integrating VLSI circuits into a 3-D dual composite module is alleviated, to some extent, by the systems disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference:
U.S. Pat. No. 4,811,082 issued to Jacobs et al;
U.S. Pat. No. 4,812,949 issued to Fonan et al;
U.S. Pat. No. 4,890,153 issued to Wu;
U.S. Pat. No. 4,901,1336 issued to Neugebauer et al;
U.S. Pat. No. 4,937,659 issued to Chall; and
U.S. Pat. No. 4,965,653 issued to Otsuka et al.
The Otsuka et al patent discloses a WSI in which a slit formed in a wafer is fit to a connector while the Chall patent discloses VLSI low cost construction. The patents to Jacobs et al, Fontan et al, Wu, and Neugebauer et al are of interest, in that they disclose VLSI and WSI state of the art technology.
While the above-cited references are instructive, none of the cited patents disclose reduction of package thickness 0.29 (in) for dual composite module in order to meet the equivalent module size, for dual composite module construction. The task of redesigning VLSI circuits so that they are integrated into 3-D dual composite modules represents a current technical need. The present invention is intended to help satisfy that need.